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| E2G0023-17-41 Semiconductor MSM514400D/DL Semiconductor This version: Jan. 1998 MSM514400D/DL Previous version: May 1997 1,048,576-Word 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM514400D/DL is a 1,048,576-word 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514400D/DL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514400D/DL is available in a 26/20-pin plastic SOJ, 20pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514400DL (the low-power version) is specially designed for lower-power applications. FEATURES * 1,048,576-word 4-bit configuration * Single 5 V power supply, 10% tolerance * Input : TTL compatible, low input capacitance * Output : TTL compatible, 3-state * Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version) * Fast page mode, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Multi-bit test mode capability * Package options: 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514400D/DL-xxSJ) 20-pin 400 mil plastic ZIP (ZIP20-P-400-1.27) (Product : MSM514400D/DL-xxZS) 26/20-pin 300 mil plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product : MSM514400D/DL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM514400D/DL-50 MSM514400D/DL-60 MSM514400D/DL-70 Access Time (Max.) tRAC tAA tCAC tOEA 50 ns 25 ns 13 ns 13 ns 60 ns 30 ns 15 ns 15 ns 70 ns 35 ns 20 ns 20 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 90 ns 110 ns 130 ns 550 mW 495 mW 440 mW 5.5 mW/ 1.1 mW (L-version) 1/17 Semiconductor MSM514400D/DL PIN CONFIGURATION (TOP VIEW) DQ1 1 26 VSS OE 1 DQ2 2 25 DQ4 23 CAS 22 OE 18 A8 17 A7 16 A6 15 A5 14 A4 DQ3 3 VSS 5 2 CAS DQ1 1 WE 3 WE 3 A9 5 A0 9 24 DQ3 4 DQ4 6 DQ1 8 WE DQ2 2 RAS 4 DQ2 7 RAS 4 A9 5 A0 9 RAS 9 A0 11 A2 13 A5 17 A7 19 10 A9 12 A1 14 A3 16 A4 18 A6 20 A8 A1 10 A2 11 A3 12 VCC 15 A1 10 A2 11 A3 12 VCC 13 VCC 13 26/20-Pin Plastic SOJ 20-Pin Plastic ZIP 26/20-Pin Plastic TSOP (K Type) Pin Name A0 - A9 RAS CAS DQ1 - DQ4 OE WE VCC VSS Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5 V) Ground (0 V) 26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE 18 A8 17 A7 16 A6 15 A5 14 A4 2/17 Semiconductor MSM514400D/DL BLOCK DIAGRAM RAS CAS Timing Generator Timing Generator 10 Column Address Buffers Internal Address Counter 10 Column Decoders Write Clock Generator WE OE 4 Output Buffers Input Buffers 4 4 A0 - A9 Refresh Control Clock Sense Amplifiers 4 I/O Selector 4 4 4 DQ1 - DQ4 10 Row Address Buffers 10 Row Decoders Word Drivers Memory Cells VCC On Chip VBB Generator VSS 3/17 Semiconductor MSM514400D/DL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA W C C *: Ta = 25C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -1.0 Typ. 5.0 0 -- -- Max. 5.5 0 6.5 0.8 (Ta = 0C to 70C) Unit V V V V Capacitance Parameter Input Capacitance (A0 - A9) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ4) Symbol CIN1 CIN2 CI/O Typ. -- -- -- (VCC = 5 V 10%, Ta = 25C, f = 1 MHz) Max. 6 7 7 Unit pF pF pF 4/17 Semiconductor DC Characteristics MSM514400D/DL (VCC = 5 V 10%, Ta = 0C to 70C) Condition MSM514400 MSM514400 MSM514400 D/DL-50 D/DL-60 D/DL-70 Unit Note Min. Max. VCC 0.4 10 Min. 2.4 0 -10 Max. VCC 0.4 10 Min. 2.4 0 -10 Max. VCC 0.4 10 V V mA 2.4 0 -10 Parameter Output High Voltage Output Low Voltage Input Leakage Current Symbol VOH IOH = -5.0 mA VOL IOL = 4.2 mA 0 V VI 6.5 V; ILI All other pins not under test = 0 V DQ disable 0 V VO 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC -0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. tRC = 125 ms, ICC10 CAS before RAS, tRAS 1 ms Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) ILO -10 10 -10 10 -10 10 mA ICC1 -- -- -- -- -- 100 2 1 200 100 -- -- -- -- -- 90 2 1 200 90 -- -- -- -- -- 80 2 1 200 80 mA 1, 2 mA mA 1 1, 5 mA 1, 2 -- 5 -- 5 -- 5 mA 1 -- 100 -- 90 -- 80 mA 1, 2 -- 80 -- 70 -- 60 mA 1, 3 -- 300 -- 300 -- 300 mA 1, 4, 5 Notes : 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC - 0.2 V VIH 6.5 V, -1.0 V VIL 0.2 V. L-version. 5/17 Semiconductor AC Characteristics (1/2) MSM514400D/DL (VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3, 11, 12 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (L-version) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time MSM514400 MSM514400 MSM514400 D/DL-50 D/DL-70 D/DL-60 Unit Note Symbol Min. Max. Min. Max. Min. Max. tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL 90 131 35 76 -- -- -- -- -- 0 0 0 3 -- -- 30 50 50 13 10 10 13 50 5 30 20 15 0 10 0 10 45 25 -- -- -- -- 50 13 25 30 13 -- 13 13 50 16 128 -- 10,000 100,000 110 150 40 80 -- -- -- -- -- 0 0 0 3 -- -- 40 60 60 15 15 10 15 60 5 35 20 15 0 10 0 15 50 30 -- -- -- -- 60 15 30 35 15 -- 15 15 50 16 128 -- 10,000 100,000 130 180 45 95 -- -- -- -- -- 0 0 0 3 -- -- 50 70 70 20 20 10 20 70 5 40 20 15 0 10 0 15 55 35 -- -- -- -- 70 20 35 40 20 -- 20 20 50 16 128 -- 10,000 100,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 4, 5, 6 4, 5 4, 6 4 4 4 7 7 3 -- -- -- 10,000 -- -- -- 37 25 -- -- -- -- -- -- -- -- -- 10,000 -- -- -- 45 30 -- -- -- -- -- -- -- -- -- 10,000 -- -- -- 50 35 -- -- -- -- -- -- 6/17 Semiconductor AC Characteristics (2/2) MSM514400D/DL (VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3, 11, 12 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) Symbol MSM514400 MSM514400 MSM514400 D/DL-50 D/DL-70 D/DL-60 Unit Note Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0 0 0 0 10 45 10 15 15 15 0 15 50 15 35 50 80 55 10 5 10 10 10 10 10 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0 0 0 0 10 50 10 20 20 20 0 15 55 20 45 60 95 65 10 5 10 10 10 10 10 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 10 10 8 8 9 0 0 0 0 10 40 10 13 13 13 0 10 45 13 36 48 73 53 10 5 10 10 10 10 10 tRCS tRCH tRRH tWCS tWCH tWCR tWP tOEH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR WE to RAS Precharge Time (CAS before RAS) tWRP WE Hold Time from RAS (CAS before RAS) tWRH RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tWTS tWTH 7/17 Semiconductor Notes: MSM514400D/DL 1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA0 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/17 E2G0094-17-41G Semiconductor MSM514400D/DL ,,, , ,,,, TIMING WAVEFORM Read Cycle tRC tRAS tRP VIH - RAS VIL - tAR tCRP tCRP tCSH tRCD CAS VIH - VIL - tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address VIH - VIL - VIH - VIL - VIH - VIL - VOH - Row Column tRCS tRRH tRCH WE OE tAA tROH tOEA tRAC tCAC tOEZ tOFF DQ VOL - Open tCLZ Valid Data-out "H" or "L" Write Cycle (Early Write) tRC tRAS tRP RAS VIH - VIL - tAR tCRP tCRP tRCD tCSH tRSH VIH - CAS VIL - VIH - VIL - VIH - tRAD tRAH tCAS tASR tASC tCAH tRAL Address Row Column tWCS tWCH tWP tCWL WE VIL - VIH - tWCR tRWL OE VIL - VIH - tDS tDHR tDH DQ VIL - Valid Data-in Open "H" or "L" 9/17 ,,, Semiconductor MSM514400D/DL Read Modify Write Cycle tRWC tRAS tRP RAS VIH - VIL - tAR tCRP tCSH tCRP tRCD tRSH VIH - CAS VIL - tCAS tASR tRAH tASC tCAH VIH - Address VIL - WE OE VIH - VIL - VIH - VIL - VI/OH- Row Column tRAD tRWD tCWD tAA tRCS tOEA tAWD tCWL tRWL tWP tOED tOEH tRAC tCAC tOEZ tDS tDH DQ VI/OL- tCLZ Valid Data-out Valid Data-in "H" or "L" 10/17 ,, , ,,, Fast Page Mode Read Cycle tRASP tRP VIH - RAS V - IL VIH - CAS VIL - VIH - VIL - VIH - VIL - tAR tRHCP tCRP tRCD tPC tRAD tCAS tCP tCAS tCP tRSH tCRP tCAS tASR tRAH tASC tCSH tCAH tASC tCAH tASC tRAL tCAH Address Row Column Column Column tRCS tRCH tRCS tAA tRCH tRCS tAA tRCH WE tAA tRRH VIH - OE VIL - tOEA tCPA tOEA tCPA tOEA tRAC tCAC tOFF tOEZ tCAC tOFF tCAC tOFF tCLZ tOEZ tCLZ tOEZ VOH - DQ VOL - tCLZ Valid Data-out Valid Data-out Valid Data-out Semiconductor MSM514400D/DL "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP tPC tRP VIH - RAS V - IL VIH - CAS VIL - VIH - VIL - VIH - VIL - VIH - VIL - tAR tRHCP tCRP tRCD tRSH tCRP tCAS tCP tCAS tCP tCAS tASR tRAH tASC tRAD tCSH tCAH tASC tCAH tASC tCAH tRAL Address Row tWCS WE Column tCWL tWCH tWP tWCR tDH Column tCWL tWCS tWCH tWP Column tRWL tCWL tWCS tWCH tWP tDS tDH tDS tDS tDH DQ Valid Data-in Valid Data-in Valid Data-in tDHR Note: OE = "H" or "L" "H" or "L" 11/17 Semiconductor Fast Page Mode Read Modify Write Cycle VIH - RAS VIL - VIH - CAS VIL - tAR Address VIH - VIL - V WE IH - VIL - VIH - OE V - IL VI/OH- VI/OL - DQ RAS-Only Refresh Cycle RAS VIH - VIL - VIH - VIL - CAS Address VIH - VIL - DQ VOH - VOL - ,,,, , , , tRASP tRP tCSH tRCD tCAS tCP tPRWC tCAS tCP tRSH tCAS tCRP tRAD tRAH tCAH tASC tASC tASR tASC tCAH tCAH tRAL Row Column tRWD Column Column tRCS tCWD tCWL tRCS tCPWD tCWD tAWD tCWL tRCS tCPWD tCWD tAWD tRWL tCWL tAWD tRAC tDS tWP tDH tDS tWP tDH tROH tDS tWP tDH tAA tCPA tAA tCPA tAA tOEA tOEA tOEA tOED tOED tOED tCAC tOEZ tCAC tOEZ In MSM514400D/DL tCAC tOEZ Out In Out Out In tCLZ tCLZ tCLZ "H" or "L" tRC tRAS tRP tCRP tRPC tASR tRAH Row tOFF Open Note: WE, OE = "H" or "L" "H" or "L" 12/17 Semiconductor CAS before RAS Refresh Cycle tRC MSM514400D/DL tRP RAS VIH - VIL - tRPC tCP CAS VIH - VIL - tWRP tWRH tCSR tCHR tRAS tRP tRPC ,,, WE VIH - VIL - VOH - VOL - tOFF DQ Open Note: OE, Address = "H" or "L" "H" or "L" tWRP Hidden Refresh Read Cycle tRC tRC tRAS tRP tRAS tRP RAS VIH - VIL - VIH - VIL - tAR tCRP tRCD tRSH tCHR CAS tASR tRAD tASC tRAH tCAH Address VIH - VIL - Row Column tRCS tRAL tRRH VIH - WE V IL - VIH - OE V IL - tAA tROH tOEA tRAC DQ VOH - VOL - tCAC tCLZ Valid Data-out tOFF tOEZ "H" or "L" 13/17 Semiconductor Hidden Refresh Write Cycle tRC tRAS RAS VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL - tAR tRP tRC tRAS MSM514400D/DL tRP CAS Address WE OE DQ Test Mode Initiate Cycle RAS CAS WE DQ , ,,,, , tCRP tRCD tRSH tCHR tASR tRAH tRAD tASC tCAH tRAL Row Column tWCS tWCH tWP tWRP tWRH tDS tDH Valid Data-in tDHR "H" or "L" tRC tRP tRAS VIH - VIL - tRPC tCP tCSR tCHR VIH - VIL - tWTS tWTH VIH - VIL - tOFF VOH - VOL - Open Note: OE, Address = "H" or "L" "H" or "L" 14/17 Semiconductor MSM514400D/DL PACKAGE DIMENSIONS (Unit : mm) SOJ26/20-P-300-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/17 Semiconductor MSM514400D/DL (Unit : mm) ZIP20-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP. 16/17 Semiconductor MSM514400D/DL (Unit : mm) TSOPII26/20-P-300-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.38 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/17 |
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